View ADG541211_5564090.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

high voltage latch-up proof, quad spst switches adg5412/ adg5413 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010C2011 analog devices, inc. all rights reserved. features latch-up proof 8 kv human body model (hbm) esd rating low on resistance (<10 ) 9 v to 22 v dual-supply operation 9 v to 40 v single-supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd analog signal range applications relay replacement automatic test equipment data acquisition instrumentation avionics audio and video switching communication systems functional block diagrams in1 s1 d1 in2 s2 d2 in 3 s3 d3 in4 s4 d4 adg5412 switches shown for a logic 1 input. in2 s2 d2 in3 s3 d3 in1 s1 d1 in4 s4 d4 adg5413 09202-001 figure 1. general description the adg5412/adg5413 contain four independent single- pole/single-throw (spst) switches. the adg5412 switches turn on with logic 1. the adg5413 has two switches with digital control logic similar to that of the adg5412; however, the logic is inverted on the other two switches. each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. the adg5412 and adg5413 do not have a v l pin. the digital inputs are compatible with 3 v logic inputs over the full operating supply range. the on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. high switching speed also makes the devices suitable for video signal switching. the adg5413 exhibits break-before-make switching action for use in multiplexer applications. product highlights 1. trench isolation guards against latch-up. a dielectric trench separates the p and n channel transistors thereby preventing latch-up even under severe overvoltage conditions. 2. low r on . 3. dual-supply operation. for applications where the analog signal is bipolar, the adg5412/adg5413 can be operated from dual supplies up to 22 v. 4. single-supply operation. for applications where the analog signal is unipolar, the adg5412/adg5413 can be operated from a single rail power supply up to 40 v. 5. 3 v logic compatible digital inputs: v inh = 2.0 v, v inl = 0.8 v. 6. no v l logic power supply required.
adg5412/adg5413 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply........................................................................ 5 36 v single supply........................................................................ 6 continuous current per channel, sx or dx..............................7 absolute maximum ratings ............................................................8 esd caution...................................................................................8 pin configurations and function descriptions ............................9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 14 terminology .................................................................................... 16 trench isolation.............................................................................. 17 applications information .............................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 6/11rev. 0 to rev. a change to i ss parameter in table 2................................................. 4 7/10revision 0: initial version
adg5412/adg5413 rev. a | page 3 of 20 specifications 15 v dual supply v dd = +15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 9.8 typ v s = 10 v, i s = ?10 ma; see figure 24 11 14 16 max v dd = +13.5 v, v ss = ?13.5 v on-resistance match between channels, ?r on 0.35 typ v s = 10 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat (on) 1.2 typ v s = 10 v, i s = ?10 ma 1.6 2 2.2 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.05 na typ v s = 10 v, v d = 10 v; see m figure 27 0.25 0.75 3.5 na max drain off leakage, i d (off ) 0.05 na typ v s = 10 v, v d = 10 v; see m figure 27 0.25 0.75 3.5 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 10 v; see figure 23 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 170 ns typ r l = 300 , c l = 35 pf 202 236 262 ns max v s = 10 v; see figure 31 t off 120 ns typ r l = 300 , c l = 35 pf 145 170 182 ns max v s = 10 v; see figure 31 break-before-make time delay, t d (adg5413 only) 15 ns typ r l = 300 , c l = 35 pf 6 ns min v s1 = v s2 = 10 v; see figure 30 charge injection, q inj 240 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 25 total harmonic distortion + noise 0.009 % typ r l = 1 k, 15 v p-p, f = 20 hz to 20 khz; see figure 28 ?3 db bandwidth 167 mhz typ r l = 50 , c l = 5 pf; see figure 29 insertion loss ?0.7 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 29 c s (off ) 18 pf typ v s = 0 v, f = 1 mhz c d (off ) 18 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 60 pf typ v s = 0 v, f = 1 mhz
adg5412/adg5413 rev. a | page 4 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = +20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 9 typ v s = 15 v, i s = ?10 ma; see figure 24 10 13 15 max v dd = +18 v, v ss = ?18 v on-resistance match between channels, ?r on 0.35 typ v s = 15 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat (on) 1.5 typ v s = 15 v, i s = ?10 ma 1.8 2.2 2.5 max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.05 na typ v s = 15 v, v d = 15 v; see m figure 27 0.25 0.75 3.5 na max drain off leakage, i d (off ) 0.05 na typ v s = 15 v, v d = 15 v; see m figure 27 0.25 0.75 3.5 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 15 v; see figure 23 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 158 ns typ r l = 300 , c l = 35 pf 187 217 240 ns max v s = 10 v; see figure 31 t off 110 ns typ r l = 300 , c l = 35 pf 138 154 170 ns max v s = 10 v; see figure 31 break-before-make time delay, t d (adg5413 only) 12 ns typ r l = 300 , c l = 35 pf 5 ns min v s1 = v s2 = 10 v; see figure 30 charge injection, q inj 310 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 32 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 25
adg5412/adg5413 rev. a | page 5 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments total harmonic distortion + noise 0.007 % typ r l = 1 k, 20 v p-p, f = 20 hz to 20 khz; see figure 28 ?3 db bandwidth 160 mhz typ r l = 50 , c l = 5 pf; see figure 29 insertion loss ?0.6 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 29 c s (off ) 17 pf typ v s = 0 v, f = 1 mhz c d (off ) 17 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 60 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 19 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 24 22 27 31 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels, ?r on 0.4 typ v s = 0 v to 10 v, i s = ?10 ma 0.8 1 1.2 max on-resistance flatness, r flat (on) 4.4 typ v s = 0 v to 10 v, i s = ?10 ma 5.5 6.5 7.5 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.05 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 27 0.25 0.75 3.5 na max drain off leakage, i d (off ) 0.05 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 27 0.25 0.75 3.5 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v/10 v; see figure 23 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 225 ns typ r l = 300 , c l = 35 pf 296 358 403 ns max v s = 8 v; see figure 31 t off 150 ns typ r l = 300 , c l = 35 pf 187 222 247 ns max v s = 8 v; see figure 31
adg5412/adg5413 rev. a | page 6 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments break-before-make time delay, t d (adg5413 only) 70 ns typ r l = 300 , c l = 35 pf 38 ns min v s1 = v s2 = 8 v; see figure 30 charge injection, q inj 95 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 32 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 25 total harmonic distortion + noise 0.07 % typ r l = 1 k, 6 v p-p, f = 20 hz to 20 khz; see figure 28 ?3 db bandwidth 180 mhz typ r l = 50 , c l = 5 pf; see figure 29 insertion loss ?1.3 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 29 c s (off ) 22 pf typ v s = 6 v, f = 1 mhz c d (off ) 22 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 58 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 10.6 typ v s = 0 v to 30 v, i s = ?10 ma; see figure 24 12 15 17 max v dd = 32.4 v, v ss = 0 v on-resistance match between channels, ?r on 0.35 typ v s = 0 v to 30 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat(on) 2.7 typ v s = 0 v to 30 v, i s = ?10 ma 3.2 3.8 4.5 max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off ) 0.05 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 27 0.25 0.75 3.5 na max drain off leakage, i d (off ) 0.05 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 27 0.25 0.75 3.5 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v/30 v; see figure 23 0.4 2 12 na max
adg5412/adg5413 rev. a | page 7 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 2.5 pf typ dynamic characteristics 1 t on 180 ns typ r l = 300 , c l = 35 pf 220 230 248 ns max v s = 18 v; see figure 31 t off 130 ns typ r l = 300 , c l = 35 pf 169 167 174 ns max v s = 18 v; see figure 31 break-before-make time delay, t d (adg5413 only) 25 ns typ r l = 300 , c l = 35 pf 8 ns min v s1 = v s2 = 18 v; see figure 30 charge injection, q inj 280 pc typ v s = 18 v, r s = 0 , c l = 1 nf; see figure 32 off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz; figure 25 total harmonic distortion + noise 0.03 % typ r l = 1 k, 18 v p-p, f = 20 hz to 20 khz; see figure 28 ?3 db bandwidth 174 mhz typ r l = 50 , c l = 5 pf; see figure 29 insertion loss ?0.8 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 29 c s (off ) 18 pf typ v s = 18 v, f = 1 mhz c d (off ) 18 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 58 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. continuous current per channel, sx or dx table 5. parameter 25c 85c 125c unit continuous current, sx or dx v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 89 59 37 ma maximum lfcsp ( ja = 30.4c/w) 160 94 49 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 95 63 39 ma maximum lfcsp ( ja = 30.4c/w) 170 98 50 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 61 43 29 ma maximum lfcsp ( ja = 30.4c/w) 110 70 42 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 80 54 35 ma maximum lfcsp ( ja = 30.4c/w) 144 87 47 ma maximum
adg5412/adg5413 rev. a | page 8 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or dx pins 278 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, sx or dx 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 16-lead tssop (4-layer board) 112.6c/w 16-lead lfcsp (4-layer board) 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c 1 overvoltages at the inx, sx, and dx pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
adg5412/adg5413 rev. a | page 9 of 20 pin configurations and function descriptions in1 1 d1 2 s1 3 v ss 4 in2 16 d2 15 s2 14 v dd 13 gnd 5 nc 12 s4 6 s3 11 d4 7 d3 10 in4 8 in3 9 nc = no connect adg5412/ adg5413 top view (not to scale) 09202-002 figure 2. tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 2. nc = no connect. pin 1 indicator 1 s1 2v ss 3 gnd 4 s4 11 v dd 12 s2 10 nc 9s3 5 d 4 6 i n 4 7 i n 3 8 d 3 1 5 i n 1 1 6 d 1 1 4 i n 2 1 3 d 2 adg5412/ adg5413 top view (not to scale) 09202-003 figure 3. lfcsp pin configuration table 7. pin function descriptions pin no. tssop lfcsp nemonic description 1 15 in1 logic control input 1. 2 16 d1 drain terminal 1. this pin can be an input or output. 3 1 s1 source terminal 1. this pin can be an input or output. 4 2 v ss most negative power supply potential. 5 3 gnd ground (0 v) reference. 6 4 s4 source terminal 4. this pin can be an input or output. 7 5 d4 drain terminal 4. this pin can be an input or output. 8 6 in4 logic control input 4. 9 7 in3 logic control input 3. 10 8 d3 drain terminal 3. this pin can be an input or output. 11 9 s3 source terminal 3. this pin can be an input or output. 12 10 nc no connection. 13 11 v dd most positive power supply potential. 14 12 s2 source terminal 2. this pin can be an input or output. 15 13 d2 drain terminal 2. this pin can be an input or output. 16 14 in2 logic control input 2. ep exposed pad the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is reco mmended that the pad be soldered to the substrate, v ss . table 8. adg5412 truth table in switch condition 1 on 0 off table 9. adg5413 truth table in s1, s4 s2, s3 0 off on 1 on off
adg5412/adg5413 rev. a | page 10 of 20 typical performance characteristics 0 2 4 6 8 10 12 14 16 ?20 ?15 ?10 10 ?5 0 5 10 15 20 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +10v v ss = ?10v v dd = +13.5v v ss = ?13.5v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v v dd = +11v v ss = ?11v 09202-034 figure 4. r on as a function of v s , v d (dual supply) 0 2 4 6 8 10 12 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09202-035 figure 5. r on as a function of v s , v d (dual supply) 0 5 10 15 20 25 0 2 4 6 8 101214 on resistance ( ? ) v s , v d (v) t a = 25c v dd = +9v v ss = 0v v dd = +10v v ss = 0v v dd = 10.8v v ss = 0v v dd = 11v v ss = 0v v dd = 13.2v v ss = 0v v dd = 12v v ss = 0v 09202-032 figure 6. r on as a function of v s , v d (single supply) 0 2 4 6 8 10 12 0 5 10 15 20 25 30 35 40 45 on resistance ( ? ) t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v v s , v d (v) 09202-033 figure 7. r on as a function of v s , v d (single supply) 0 2 4 6 8 10 12 14 18 16 ?15 ?10 ?5 0 5 10 15 on resistance ( ? ) v s , v d (v) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = +15v v ss = ?15v 09202-040 figure 8. r on as a function of v s (v d ) for different temperatures, 15 v dual supply 0 2 4 6 8 10 12 14 16 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance ( ? ) v s , v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09202-041 figure 9. r on as a function of v s (v d ) for different temperatures, 20 v dual supply
adg5412/adg5413 rev. a | page 11 of 20 0 5 10 15 20 25 30 024681012 on resistance ( ? ) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v v s , v d (v) 09202-042 figure 10. r on as a function of v s (v d ) for different temperatures, 12 v single supply 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 on resistance ( ? ) v s , v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09202-043 figure 11. r on as a function of v s (v d ) for different temperatures, 36 v single supply 0 255075100125 leakage current (na) temperature (c) 0.4 0.2 ?0.2 0 ?0.4 0.6 0.8 v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09202-037 figure 12. leakage currents vs. temperature, 15 v dual supply 0 25 50 75 100 125 leakage current (na) temperature (c) 0.4 0.2 ?0.2 0 ?0.6 ?0.4 0.6 0.8 v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09202-038 figure 13. leakage currents vs. temperature, 20 v dual supply 0 255075100125 leakage current (na) temperature (c) 0.4 0.2 ?0.2 0 0.6 v dd = 12v v ss = 0v v bias = 1v/10v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09202-036 figure 14. leakage currents vs. temperature, 12 v single supply 0 25 50 75 100 125 leakage current (na) temperature (c) 0.4 0.2 ?0.2 0 ?0.4 ?0.6 0.6 0.8 v dd = 36v v ss = 0v v bias = 1v/30v i d , i s (on) + + i d , i s (on) ? ? i s (off) + ? i d (off) ? + i d (off) + ? i s (off) ? + 09202-039 figure 15. leakage currents vs. temperature, 36 v single supply
adg5412/adg5413 rev. a | page 12 of 20 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 off isol a tion (db) frequency (hz) 10k 100k 1m 10m 100m 1g 1k t a = 25c v dd = +15v v ss = ?15v 09202-025 figure 16. off isolation vs. frequency, 15 v dual supply ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 crosstalk (db) frequency (hz) 10k 100k 1m 10m 100m 1g t a = 25c v dd = +15v v ss = ?15v 09202-028 figure 17. crosstalk vs. frequency, 15 v dual supply 0 50 100 150 200 250 300 350 400 450 500 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09202-030 figure 18. charge injection vs. source voltage acpsrr (db) frequency (hz) 1k 1m 10m 10k 100k ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 t a = 25c v dd = +15v v ss = ?15v decoupling capacitors no decoupling capacitors 09202-026 figure 19. acpsrr vs. frequency, 15 v dual supply 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 5 10 15 20 thd + n (%) frequency (mhz) load = 1k ? t a = 25c v dd = 12v, v ss = 0v, v s = 6v p-p v dd = 36v, v ss = 0v, v s = 18v p-p v dd = 15v, v ss = 15v, v s = 15v p-p v dd = 20v, v ss = 20v, v s = 20v p-p 09202-027 figure 20. thd + n vs. frequency, 15 v dual supply ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 insertion loss (db) frequency (hz) 10k 100k 1m 10m 100m 1k 1g t a = 25c v dd = +15v v ss = ?15v 09202-029 figure 21. bandwidth
adg5412/adg5413 rev. a | page 13 of 20 09202-031 0 50 100 150 200 250 300 350 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) t off (15v) t off (36v) t off (20v) t on (20v) t on (15v) t on (36v) t on (12v) t off (12v) figure 22. t on , t off times vs. temperature
adg5412/adg5413 rev. a | page 14 of 20 test circuits v d sx dx v s a i d (on) 09202-016 figure 23. on leakage sx dx v s v1 i ds r on = v 1 /i ds 09202-014 figure 24. on resistance channel-to-channel crosstalk = 20 log v out gnd s1 dx s2 v out network analyzer r l 50? r l 50 ? v s v s v dd v ss 0.1f v dd 0.1f v ss 09202-021 figure 25. channel-to-channel crosstalk v out 50 ? network analyzer r l 50? inx v in sx dx 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 09202-020 figure 26. off isolation sx dx v s a a v d i s (off) i d (off) 09202-015 figure 27. off leakage v dd v ss v dd v ss v out r s audio precision r l 1k? inx v in sx dx v s v p-p 0.1f 0.1f gnd 09202-024 figure 28. thd + noise v out 50? network analyzer r l 50? inx v in sx dx insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 09202-023 figure 29. bandwidth
adg5412/adg5413 rev. a | page 15 of 20 v s2 in1, in2 s2 d2 v s1 s1 d1 gnd r l 300 ? c l 35pf v out2 v out1 v dd v ss 0.1f v dd 0.1f v ss v in v out1 v out2 adg5413 t d t d 50% 50% 90% 90% 90% 90% 0v 0v 0v r l 300 ? c l 35pf 09202-017 figure 30. break-before-make time delay, t d v s inx sx dx gnd r l 300 ? c l 35pf v out v dd v ss 0.1f v dd 0.1f v ss adg5412 v in v out t on t off 50% 50% 90% 90% 09202-018 figure 31. switching times in v out adg5412 v in v out off ? v out on q inj = c l ? v out sx dx v dd v ss v dd v ss v s r s gnd c l 1nf 09202-019 figure 32. charge injection
adg5412/adg5413 rev. a | page 16 of 20 terminology i dd i dd represents the positive supply current. i ss i ss represents the negative supply current. v d , v s v d and v s represent the analog voltage on terminal d and ter mina l s, resp e c t ively. r on r on represents the ohmic resistance between terminal d and ter mina l s. r on r on represents the difference between the r on of any two channels. r flat (on) flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital inputs. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in is the digital input capacitance. t on t on represents the delay between applying the digital control input and the output switching on. t off t off represents the delay between applying the digital control input and the output switching off. t d t d represents the off time measured between the 80% point of both switches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off switch. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is the frequency at which the output is attenuated by 3 db. on response on response is the frequency response of the on switch. insertion loss insertion loss is the loss due to the on resistance of the switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by thd + n. ac power supply rejection ratio (acpsrr) acpsrr is the ratio of the amplitude of signal on the output to the amplitude of the modulation. this is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p.
adg5412/adg5413 rev. a | page 17 of 20 trench isolation in the adg5412 and adg5413, an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse-biased under normal operation. however, during overvoltage conditions, this diode can become forward-biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. with trench isolation, this diode is removed, and the result is a latch- up proof switch. 09202-022 nmos pmos p-well n-well buried oxide layer handle wafer trench figure 33. trench isolation
adg5412/adg5413 rev. a | page 18 of 20 applications information the adg54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. the adg5412/adg5413 high voltage switches allow single-supply operation from 9 v to 40 v and dual-supply operation from 9 v to 22 v. the adg5412/adg5413 (as well as other select devices within the same family) achieve an 8 kv human body model esd rating, which provides a robust solution eliminating the need for separate protect circuitry designs in some applications.
adg5412/adg5413 rev. a | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 34. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.45 0.40 0.35 s eating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 35. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-17) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5412bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5412bruz-reel7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5412bcpz-reel7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-17 adg5413bruz ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5413bruz-reel7 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg5413bcpz-reel7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-17 1 z = rohs compliant part.
adg5412/adg5413 rev. a | page 20 of 20 notes ?2010C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09202-0-6/11(a)

▲Up To Search▲

Price & Availability of ADG541211

	To Download ADG541211 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .